This invention relates, in general, to semiconductor components and, more particularly, to extension-gate edge overlap in a semiconductor component.
Integrated circuits such as microprocessors, digital signal processors, microcontrollers, memory devices, and the like typically contain millions of Insulated Gate Field Effect Transistors (IGFETs). Because of the desire to lower manufacturing costs and increase circuit speed, integrated circuit manufacturers shrink the sizes of the IGFET""s making up an integrated circuit so that more integrated circuits can be manufactured from a single semiconductor wafer. Although the smaller transistors are capable of operating at increased speeds, secondary performance factors such as decreased source-drain breakdown voltage, increased junction capacitance, and instability of the threshold voltage negatively affect transistor performance. Collectively, these adverse performance effects are referred to as short channel effects.
Typical techniques for mitigating short channel effects rely on adjusting the electric field in the channel region to minimize the peak lateral electric field of the drain depletion region. One technique for lowering the lateral electric field is to include source and drain extension regions. A source extension region extends into a silicon substrate adjacent one side of a gate structure and a drain extension region extends into the silicon substrate adjacent an opposing side of the gate structure. The source and drain extension regions extend under the gate structure. The drain extension region reduces the maximum electric field in the drain region of an insulated gate field effect transistor, thereby reducing the number of electrons capable of tunneling from the drain region into the gate oxide. Even with this improvement, the number of electrons in the drain region is still sufficient to create a gate-to-drain tunneling current that decreases the performance of the transistor.
Accordingly, what is needed is a semiconductor component having a lower gate-to-drain tunneling current and a method for manufacturing the semiconductor component.
The present invention satisfies the foregoing need by providing a semiconductor component and a method for manufacturing the semiconductor component having a source-side halo region formed before the source and drain extension regions and the source and drain regions are formed. In accordance with one aspect, the present invention comprises a gate structure formed on a semiconductor material of a first conductivity type. After formation of the gate structure, a source-side halo region is formed in the semiconductor material proximal a source side of the gate structure using an ion implantation technique. After formation of the source-side halo region, a first set of spacers is formed on opposing sides of the gate structure followed by implanting a dopant of a second conductivity type using a tilt angle implant to form the source and drain extension regions. A second set of spacers is formed adjacent the first set of spacers and source and drain regions are formed in the semiconductor material.
In accordance with another aspect, the present invention comprises a semiconductor material having a gate structure disposed thereon. A source-side halo region is proximal the source side of the gate structure. A source extension region is proximal the first side of the gate structure and extends under the gate structure and a drain extension region is proximal the second side of the gate structure and may extend under the second side of the gate structure. A source region is proximal and spaced apart from the first side of the gate structure and a drain region is proximal and spaced apart from the second side of the gate structure.